Capacitive coupling is an issue in NAND Flash where the writing of a cell (accomplished by injecting charge onto the floating-gate of a cell) adds charge to the floating-gates of one or more adjacent cells. As NAND Flash process geometry is reduced, the spacing between NAND cells is reduced, thus exacerbating this effect. Techniques which are able to mitigate capacitive coupling in floating-gate cells would be desirable. In some cases, these new techniques may have application in other fields.